The present invention relates to phase lock loops and, more particularly, to a phase locked loop circuit for reducing lock-in time.
Phase locked loops (PLLs) are found in a myriad of electronic applications such as communication receivers and clock synchronization circuits for computer systems. FIG. 1 is a schematic block diagram illustrating a conventional differential PLL circuit. The PLL circuit includes a phase detector 10, a charge pump 20, a loop filter 30, and a voltage controlled oscillator (VCO) 40.
The phase detector 10 monitors the phase difference between an input signal IN to the PLL circuit and an output signal OUT from the PLL circuit, the output signal OUT being fed back from the voltage controlled oscillator (VCO) 40. The phase detector 10 also generates up control signals up and {overscore (up)}, and down control signals dn and dn for input to the charge pump circuit 20. The charge pump 20 can be implemented as a current pump or a voltage pump. The charge pump 20 charges and discharges the loop filter 30 with a pair of charge pump signals VOP and VON.
The charge pump signals VOP and VON are subsequently filtered by the loop filter 30, which is typically constructed as a low pass filter. The loop filter 30 also assists in removing or reducing high frequency components and clock jitter. Signals VOPxe2x80x2 and VONxe2x80x2 are output from the loop filter 30 to the VCO 40. The variable oscillator 40 can be implemented as a voltage controlled oscillator(VCO) or a current controlled oscillator. The VCO 40 oscillates in response to the filtered signals VOPxe2x80x2 and VONxe2x80x2. The output oscillation of the VCO 40 is the output signal OUT. When the PLL circuit is phase locked, the output signal OUT will be locked at the desired output frequency.
In general, practical limits of the output frequency range are often defined by dynamic loop characteristics underlying the PLL circuit. The loop characteristics include loop variables such as loop bandwidth, natural frequency, damping factor, among others. Values of the loop characteristics are typically based upon present parameters of component parts for the PLL circuit. The present parameters typically prevent frequency synthesis outside a predefined range of the PLL.
It is common for the PLL to lose phase lock when the input signal IN fades or jumps to a radically different frequency of operation. The out-of lock state can be detected with a lock detection circuit (not shown) and the system processing suspended until the PLL circuit can re-achieve phase lock. The transition time from the unlocked state to the locked state is referred to as the lock-in time or pull-in time. The lock-in time consists of a common mode voltage reaching time of the filtered signals VOPxe2x80x2 and VONxe2x80x2, and a tracking time of the phase detector 10. The common mode voltage reaching time occupies the major part of the lock-in time.
Thus, to reduce the common mode voltage reaching time, the current from the charge pump 20 is increased, or a time constant (i.e., xcfx84=RC) of the loop filter 30 is decreased. The time constant xcfx84 may be reduced by adjusting the resistor R or the capacitor C of the loop filter 30, so that they charge more quickly. However, the loop bandwidth increases in proportion to the reduction of the time constant. In that case, the high frequency components are not filtered sufficiently by the loop filter 30 in proportion to the increase in loop bandwidth. Furthermore, the loop characteristics of the PLL circuit vary with respect to the designed loop characteristics. Therefore, the PLL circuit cannot operate stably.
As described above, it is difficult to shorten the lock-in time because of the need to maintain the loop characteristics of the PLL circuit for stable operation thereof.
It is therefore an object of the present invention to provide a phase locked loop circuit for reducing a lock-in time.
It is another object of the invention to provide a differential phase locked loop circuit for reducing the lock-in time.
According to an aspect of the present invention, there is provided a phase locked loop (PLL) circuit for generating an output signal in response to an input signal. The PLL circuit includes a phase detector for detecting a phase error between the input signal and the output signal and outputting a pump up signal and a pump down signal based on the phase error. A charge pump coupled to the phase detector generates a charge pump signal in response to the pump up and the pump down signals. A loop filter coupled to the charge pump filters out high-frequency components from the charge pump signal to generate a filtered signal. The loop filter has an input terminal and an output terminal. A boost-up device coupled to the output terminal of the loop filter charges the input terminal of the loop filter in response to the filtered signal, to expedite the filtered signal reaching a predetermined common mode voltage level. A voltage-controlled oscillator coupled to the output terminal of the loop filter and the phase detector generates the output signal in response to the filtered signal.
According to another aspect of the present invention, there is provided a differential phase locked loop (DPLL) circuit for generating an output signal in response to an input signal. The DPLL includes a phase detector for detecting a phase error between the input signal and the output signal, and outputting a pair of pump up signals and a pair of pump down signals based on the phase error. A charge pump coupled to the phase detector generates a pair of charge pump signals in response to the pump up and the pump down signals. A loop filter coupled to the charge pump filters out high frequency components from the charge pump signals to generate a first and a second filtered signal. The loop filter has two input terminals and two output terminals. A boost-up device coupled to the output terminals of the loop filter charge the input terminals of the loop filter in response to the first and the second filtered signals, to expedite the first and the second filtered signals reaching a predetermined common mode voltage level. A voltage-controlled oscillator coupled to the output terminals of the loop filter and the phase detector generates the output signal in response to the first and the second filtered signals.